This application is based upon and claims priority from prior French Patent Application No. 99-05328, filed Apr. 23, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention generally relates to memory devices, and more specifically to a method for optimizing memory read cycles of memory devices.
2. Description of Related Art
Generally, a read operation on a memory provides data on bit lines at an unknown time after a read control signal. The bit lines must be precharged before each read operation and, when two readings are performed in a row, the precharge necessary for the second reading must be started after the end of the first reading, that is, at an unknown time after the signal controlling the first reading.
FIG. 1 schematically shows a memory 1 formed of memory cells 2 arranged in rows and columns. The cells of each row are selected by a respective row line 3, and the cells of each column are accessible in the read mode by a respective pair of complementary bit lines 4. Each pair of bit lines 4 is associated with a respective read amplifier 5 and each bit line is connected to a supply line Vdd via a precharge transistor 6. Row lines 3 are connected to a decoder 7 that receives an address A via a latch 8 rated by a read control clock signal CK. Precharge transistors 6 are controlled by a same precharge signal P. Read amplifiers 5 generate an output signal O.
To perform a reading, transistors 6 are first turned on for a duration sufficient to precharge complementary bit lines 4 to voltage Vdd, then transistors 6 are turned off and a row line 3 is activated by decoder 7. Each pair of bit lines is then unbalanced according to the information stored in the cell of the selected row. When two read operations are performed in a row, the precharge that must come before the second reading deletes the data generated by the first reading. Thus, it is necessary to guarantee that the precharge for a current read operation is always performed after the end of the preceding read operation.
The function of a reference column 9 will be described hereafter. FIG. 2 shows a memory of the type in FIG. 1, the precharge control signal P of which is obtained by inverting clock CK that rates the read operations.
FIG. 3 illustrates read operations on the circuit of FIG. 2. At a time t0, address A provided to memory 1 changes. At a time t1 that corresponds to the next rising edge of clock signal CK, address A is provided to decoder 7 by latch 8. From time t1 on, corresponding to the beginning of a read operation, output O of the memory starts changing and its state is undetermined (X). Output O is assumed to remain in an undetermined state for an unknown duration xcex94 that corresponds to the response time of the slowest column of memory 1.
At a time t2, at the end of duration xcex94, output O is assumed to be stable and it can be used. From a time t3 on, corresponding to the next rising edge of control signal P, the precharge necessary to the next read operation starts. Output O is undetermined during the entire precharge interval, which here lasts until the next rising edge of clock signal CK. It should be noted that output O generated in a read cycle starting at time t1 is stable and useable only between times t2 and t3. Time t2 depends on maximum read duration xcex94, which is a characteristic of memory 1. Time t3 depends on duration t3xe2x88x92t1, that is, on the duty cycle of signal CK.
FIG. 3 shows a signal CK with a duty cycle of one half, but it should be noted that if the latter decreases, duration t3xe2x88x92t1 also decreases and may even become smaller than duration xcex94, in which case output O is deleted before being readable. Thus, in the case where precharge signal P is the complement of clock signal CK, a minimum value of the duty cycle of signal
CK has to be guaranteed, which is not always possible. It has thus been sought to generate a precharge control signal P independent from the duty cycle of clock signal CK.
FIG. 4 shows a memory 1 of the type in FIG. 1, the precharge control signal P of which is obtained by delaying clock signal CK with a delay line D. FIG. 5 illustrates successive read operation on the circuit of FIG. 4. tD designates the delay introduced by delay line D: precharge control signal P is activated at a time t4 occurring at a duration tD after time t1. Output O generated in a read cycle that starts at a time t1 is useable between above-mentioned time t2, which depends on duration xcex94, and time t4, which depends on duration tD of delay line D. The duty cycle of clock signal CK has no influence upon duration t4xe2x88x92t2. However, duration xcex94 and delay tD vary according to the manufacturing method used, to temperature, as well as to other parameters. It is difficult to know these variations in advance, and a delay tD greater than necessary is chosen, to guarantee that duration t4xe2x88x92t2 will always be sufficient to use output O.
Delay tD must however remain smaller than one period of signal CK, so that the precharge can occur during the read cycle. Thus, if delay tD is too long, the maximum operating frequency, and thus, the performances of memory 1, have to be limited. It has thus been sought to provide a precharge control signal P with a delay that depends on the features of the memory. For this purpose, in FIG. 1, a reference column 9, of same structure as a normal column and arranged at the distal end of precharge and row lines 3, has been provided. With this configuration, reference column 9 is the latest one to provide a stable output O1 during a read operation.
FIG. 6 shows a memory of this type, the precharge control signal P of which is generated based on output O1 of the reference column by an edge detector 11. FIG. 7 illustrates read operations on the circuits of FIG. 6. Signal O1 is generated at a time t5, responsive to the edge of signal CK of time t1. xcex941 designates the duration elapsed between times t1 and t5. For the previously discussed reasons, duration xcex941 is always greater than duration xcex94, whatever the features and operating conditions of memory 1.
Edge detector 11 generates precharge control signal P responsive to signal O1 at a time t6. xcex942 designates the duration between times t5 and t6. It mainly depends on the propagation time of signal O1 and on precharge control signal P. Duration xcex942 is relatively long, since the terminal that generates signal O1 is far from the input terminals, especially from that on which precharge control signal P is provided. Durations xcex941 and xcex942, which correspond to the memory width, increase with the size thereof. Now, the sum of durations xcex941 and xcex942 must remain smaller than one period of signal CK so that the precharge occurs in the read cycle. Thus, the larger a memory, the longer duration xcex941+xcex942, and the longer the period of signal CK has to be chosen, which limits the memory performances.
Thus, there is a need to overcome the disadvantages of the prior art as discussed above, and particularly to handle the problem of unknown delays during memory read cycles.
In view of these drawbacks, in accordance with an aspect the present invention it is intended to overcome the above-mentioned drawbacks and to provide, based on a clock signal, a precharge control signal that enables optimizing the memory reading rate.
A preferred embodiment of the present invention provides an integrated circuit generating an event responsive to an edge of an input signal and with an unknown delay, which includes means for providing an internal signal including several delay lines of different sizes that receive the edge of the input signal, a multiplexer, each input of which receives the output of one of the delay lines and the output of which generates the internal signal, and a multiplexer control circuit for selecting a delay line to provide the internal signal as soon as possible after the unknown delay.
According to an alternative preferred embodiment of the present invention, the integrated circuit includes at least one reference element that generates at least one reference edge responsive to the edge of the input signal with a delay greater than the unknown delay, and the control circuit includes several comparators each receiving on a first input the output of a respective delay line and on a second input the at least one reference edge, and a circuit for analyzing the comparator outputs that controls the multiplexer to change the delay line selected during the test when the outputs of the comparators indicate a variation of the duration between the output of the selected delay line and the at least one reference edge.
According to a further alternative preferred embodiment of the present invention, the integrated circuit includes an array of memory cells selected by rows by an address signal and accessible in the read mode by columns by bit lines, the input signal is a clock signal for synchronizing the address signal, the event is the reading of a column, and the internal signal is a signal of precharge of the bit lines.
According to an additional preferred embodiment of the present invention, the integrated circuit includes an array of memory cells selected by rows by an address signal and accessible in the read mode by columns by bit lines, the input signal is a clock signal for synchronizing the address signal, the event is the reading of a column, the internal signal is a signal of precharge of the bit lines, and the at least one reference element is an additional column located with respect to the other columns so that its reading is slower than the reading of the other columns.
Further, the present invention also provides a method of setting the above-mentioned circuit, including the steps of, in a test mode:
a) selecting the shortest delay line,
b) providing the circuit with a predetermined input signal,
c) if the internal signal generated by the multiplexer occurs after the event generated responsive to the edge of the input signal, leaving the test mode,
d) otherwise selecting the immediately longer delay line and repeating steps b) and c).
Other features and advantages of the preferred embodiments of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the spirit of the present invention.